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Up Counter (Program for 4-bit binary counter using behavior description). In this program an up counter has a 1- bit input and a 4- bit output. Jan 19, 2014 - Program Counter using VHDL for Altera DE2 Board. Hi guys noob here, first post. I need to design a program counter to satisfy the following.
I am currently in the middle of a project where I am attempting to design a single cycle cpu. I am doing this without any pipe-lining, since that would greatly add to the complexity of the design. I am simply taking baby steps as I learn this. I find myself stuck at this portion where I am simply attempting to code a Program Counter(PC) using previously made components.
The model of my design looks like this picture here. Sorry, no idea why it came out dark, but if you click on it it shows correctly. The PC and theMUX are both 32 bit components, so I assume the adder is as well.
Here is the code I have been given, my implementation begins at the begin statement on line 41.Pay no attention to it for now, its just a bunch of random gibberish I was attempting.
I am fairly new to this so I have only a faint idea of how signals work, and no idea how I am supposed to implement the components into the design. I am also confused that I wasnt asked to build the adder ahead of time. Is it now necessary to use it as a component im guessing?
Anyhow, I have attempted different things that stumbled upon searching, such as the port mapping you see. But I always get some sort of error, currently the error im receiving is that objects Q, clr, and D are used but not declared. How do I declare them?If I get rid of those statements, the error simply repeats for objects X0, X1, and Y.Any help in the right direction would be greatly appreciated. Thanks guys!
Also, just in case you need them,The register
and the MUX
EDITOk, NO idea if I did this correctly, but I rewrote the portmaps. I was having errors of port names (sel, clk, X0, X1..etc) being 'used but not initialized. So that is why clr, clk and ld have initial values. Once again, no idea if that is correct, but it made the errors go away. I also realized I never added the register32 and mux2to1_32 VHDL files to my project, and after doing so got rid of the other errors I was having.
So as stands, the code compiles, I have included in the project a VWF simulation file for testing, but I KNOW the results are gonna be incorrect.
I dont know everything that is wrong yet, but I know I need to do something with PC_add_4. THis value needs to basically be (PC_current + 4), but Im not sure how to do this.
Here is the updated portion of code(everything else is the same)
And, in case they help, my list of errors..im guessing the pin related errors are because I dont have any hardware assignments made yet.
- Warning (10541): VHDL Signal Declaration warning at pc_update.vhd(38): used implicit default value for signal 'PC_add_4' because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
- Warning (10492): VHDL Process Statement warning at pc_update.vhd(61): signal 'clk' is read inside the Process Statement but isn't in the Process Statement's sensitivity list
- Warning: Output pins are stuck at VCC or GND
- Warning: Design contains 34 input pin(s) that do not drive logic
- Warning: Found 32 output pins without output pin load capacitance assignment
- Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
- Warning: Can't generate programming files because you are currently using the Quartus II software in Evaluation Mode
- Warning: No paths found for timing analysis
- Critical Warning: No exact pin location assignment(s) for 66 pins of 66 total pins
SECOND EDITSo yeah I fixed up my code by adding PC_add_4 <= (PC_current + 4 );after the port mappings, and adding 'clk' to the process sensitivity list.However my waveforms in my simulation are still wrong I believe, as shown here.
It appears to be treating incH_lDL as a clear signal, rather than simply passing PCInput to InstrAddr. This is most likely due to my setting of it to a default '0' in the port map. I did this earlier because it was giving me 'used but not declared' errors. Ill try messing with it and post my findings.
Third EDIT
I have edited my code as such:
My simulation now shows that when incH_lDL = 0, PCInput is loaded into InstrAddr, however, when incH_lDL = 1, it simply loads the value '4', and doesnt increment at the start of every clock cycle like its supposed to...I need to make use of PC_current, but I am not sure how....sicne you cant assign one signal to another like 'PC_current <= PCInput'. I will try some more things,in the mean time, any pointers would be greatly appreciated.
FOURTH EDITTHanks to anyone still reading this, and bearing through all the reading.
I have attempted to use PC_next and PC_current in my implementation, but have run into 'multiple constant drivers for net 'PC_next' errors.
MY process code:
I am aware that this error comes when these assignments are made within loops? I am truly at a loss here at what to try next.
Erik Machorro
Erik MachorroErik Machorro
1 Answer
Your port maps in the first code need to be ported to signals. You are placing the port names of the components in the port map, which is incorrect. What you would like to do is create signals that can connect those components, and place them in the port map fields instead (to match the connections in your image).
blueprintblueprint
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